Recently, rewritable non-volatile memories have been widely used for many electronic devices such as mobile phone terminals and digital cameras. FIG. 1 is a view illustrating a cross-section of a non-volatile memory cell 12 having a floating gate as a charge storage layer. In FIG. 1, an n-type well 31 is formed in a semiconductor substrate 30, and a p-type well 32 is formed on the n-type well 31. A well 33 is composed of the n-type well 31 and the p-type well 32. An n-type source region 34 and a drain region 36 are formed on the p-type well 32. A tunnel oxide film 42, a floating gate 44, an insulating film 46, and a control gate 48 are formed on the p-type well 32 between the source region 34 and the drain region 36. The control gate 48 is connected to a word line (not shown). An n-electrode 38 for applying a voltage to the n-type well 31 is formed and connected to the n-type well 31. A p-electrode 40 for applying a voltage to the p-type well 32 is formed and connected to the p-type well 32.
When a writing operation to the memory cell 12 is performed by accumulating a charge in the floating gate 44, an electric field is applied between the source region 34 and the drain region 36. A positive electric potential is applied to the well 33 via the control gate 48 and the word line. Thereby, hot electrons are injected into the floating gate 44, and a charge is accumulated in the floating gate 44. On the other hand, when an erasing operation is performed to the memory cell 12, that is, when the charge is erased from the floating gate 44, a negative electric potential is applied to the well 33 via the control gate 48 and the word line. Thereby, due to a Fowler-Nordheim tunneling phenomenon, electrons in the floating gate 44 tunnel to the p-type well 32 through the tunnel oxide film 42, thus erasing the charge in the floating gate 44.
FIG. 2 is a timing chart of a voltage Vwell of the well 33 (e.g., the n-type well 31 and the p-type well 32) and a voltage Vword of the word line (control gate) during the erasing operation. At t0, erasing of the memory cell 12 starts. The word line voltage Vword of a selected word line gradually increases in a negative direction. The well voltage Vwell gradually increases in a positive direction. At t1, the word line voltage Vword becomes a constant voltage Vword0. At t2, the well voltage Vwell becomes a constant voltage Vwell0. When the erasing of the memory cell 12, which is connected to the selected word line, is completed at t3 or later, the word line voltage Vword gradually becomes 0. At t4 or later, the well voltage Vwell gradually becomes 0.
However, between t0 and t2, the word line voltage Vword may be raised to 0V as in point A of FIG. 3 rather than being continually decreased. This may be due to capacitive coupling between the well 33 and the word line WL arranged on the well 33. Since the well 33 is commonly provided in many memory cells 12, an electrostatic capacitance (parasitic capacitance) of the well 33 is extremely large compared to that of the word line WL. Accordingly, the word line voltage Vword may be raised when the well 33 is charged. Due to the rise of the word line voltage Vword, the word line voltage Vword may not reach the constant voltage Vword0 at t1, which is the voltage that the word line voltage Vword is supposed to reach. Instead, word line voltage Vword may be kept constant at a voltage Vword0′ at t1. The disruption of the potential between the well voltage Vwell and the word line voltage Vword due to the capacitive coupling may delay and/or disrupt the erasing operation of the memory cell 12.